In general, digital data communication systems may be categorized as synchronous or asynchronous. With a synchronous system, there is a fixed number of input data bits in each frame of the transmission channel. It is therefore apparent that there must be a fixed relationship between the input data or source clock and the clock of the transmission channel. Typically, this is provided by phase locking the source clock and the transmission channel clock. In the case where there are a plurality of input data sources or groups which are multiplexed into a higher rate transmission channel or supergroup, each group clock is assigned a fixed fraction of the bits of the supergroup and therefore each must be a fixed fraction of the supergroup rate.
In many applications, it is impossible or at least impractical to phase lock the input data clock to the transmission channel clock. Accordingly, asynchronous systems are in widespread usage. Generally, they may be defined as systems where the actual input rate and the nominal expected input rate of the data channel differ. The typical treatment for this type of data stream is to run the transmission channel at a higher rate than nominal by at least the maximum anticipated input rate deviation and then selectively pulse stuff dummy bits into designated bit positions in the input data stream to increase its rate to the transmission channel rate. Generally, a stuff code which indicates whether the designated stuff bit position or positions of the frame contain actual or dummy data is transmitted in the overhead of the channel. At the receiver side of the transmission channel, the dummy bits are removed in accordance with the stuff codes. Accordingly, it is common in communication systems to receive digital data where the bits are not in a contiguous periodic stream. Stated differently, received digital data frequently has data bits not present in bit positions because of the deletion of stuffed dummy bits, the deletion of channel overhead, or the demultiplexing of transmission channel data bits to another receiver channel. Typically, the data at the receiver is stored in an elastic buffer such as a first-in first-out memory. Because it is generally preferable and sometimes necessary that the data be transferred smoothly to a user device, there may be a requirement to generate clocking pulses that will read data smoothly out of the elastic buffer. The field of the invention relates generally to the reception and reclocking of asynchronous data.
In the prior art, the pulses for clocking data smoothly out of an elastic buffer have been provided by a voltage controlled oscillator which is controlled by a filtered phase detector output. The function of the phase detector in general terms is to compare the rate at which data is stored in the elastic memory with the rate at which it is read out and then to adjust the read out rate with a particular time constant such that the long term rates are the same. The most common prior art implementation of this principle is a phase-locked loop deriving its phase error input for the filter to the voltage controlled oscillator by sampling the store half full flag. More specifically, the up input of an up/down counter may be connected to the clock reading data into a first-in first-out memory and the down input connected to the voltage controlled oscillator output which clocks data out. The count in the up/down counter therefore is related to the occupancy of the first-in first-out memory. Accordingly, the up/down counter is configured so as to provide a high voltage (logical 1) output if the first-in first-out memory is less than half full and a low voltage (logical 0) output if the first-in first-out memory is half full or more. The logical output voltage of the up/down counter is then filtered and coupled to the voltage controlled oscillator. Accordingly, if the first-in first-out memory is less than half full, the rate at which data is read out is generally decreased and if it is half full or more, it is increased. The phase error may be sampled at the stuff opportunity time so as to eliminate the stuff opportunity rate as an output jitter component. A problem with this prior art approach is that it involves very careful selection of the phase lock loop parameters. In applications involving flexibility of clock rates and stuff opportunity rates as in most programmable multiplexers, it is difficult to attain the variable phase lock loop parameters.
Another prior art method for providing a smooth clock is to alternate between two clocks, one above nominal by more than the maximum input rate deviation and the other below nominal by the same amount. The actual clock oscillator rates may be chosen so as to reduce potential phase discontinuities at the switching time. If the elastic buffer is half full or more, the higher rate oscillator is selected causing store depletions. When the store becomes less than half full, the lower rate clock is selected allowing the store to again fill. This method, although simple, results in an output clock with no strong component within the input clock error band. Accordingly, subsequent narrow band filtering such as crystal filters may see no clock at all. In other words, the generator clock may not pass a narrow band filter in a user device because the band may be between the two clock oscillators or at least not contain them both.